This invention relates generally to the field of chip design and more particularly to a method for multi-cycle path and false path clock gating.
Semiconductor chips are composed of complex electronic circuit arrangements. With each progressive generation of semiconductor technology the on-chip power utilized radically increases. Accordingly, one concern to chip designers is the limitation of power consumption. In order to reduce the chip power consumption, various circuit and architectural techniques have been employed. Both dynamic power and static power are of significant concern in today's technologies. Dynamic power is the power that is generated due to switching on the semiconductor chip. Static power consumption has increased with each new technology due to higher leakage currents. These leakage currents lead to a large amount of standby or static current, even though no switching is taking place.
One method for reducing dynamic power has been the reduction of the chip cycle rate since chips consume less power when operating at lower frequencies. Operating a chip at a slower speed, however, leads to a corresponding lower performance. Lower performance is not a viable option given the insatiable customer demand for higher performance, and thus greater processing power. Another method for improving chip power consumption has been the reduction of power supply voltage across the entire chip. Since chip power is proportional to the square of the supply voltage, any reduction in power supply voltage has a radical impact on reducing the power consumption. However, as the supply voltage is reduced the performance also reduces, creating a dilemma for the chip designer. In order to save power without adversely impacting the chip performance, chips have been segmented into different portions with different power supplies depending on the performance requirement. Power may also be saved by selectively shutting off power supplies to logic when it is not being utilized. A large block of logic may be shut down or individual gates or groups of gates may be shut down. An MTCMOS library is designed so that individual gates may be powered down as desired by an appropriate control signal.
A further concept that has been utilized to save power is clock gating. By gating the clock, switching power is reduced. The decision to perform clock gating and what logic circuits to gate has typically been a laborious, designer intensive job. Given this significant effort and the fact that the amount of on chip logic has grown radically, obtaining a truly optimal gating arrangement has become problematic. It is highly unlikely for any designer to identify all of the circuit portions which can be clock gated to save power and to properly implement the clock gating. Further, a clock gating circuit itself occupies chip area and consumes additional power.
Clock gating of certain types of circuitry is more difficult than others. Multi-cycle paths and false paths are among these types of circuits and a progressively larger portion of on-chip circuits constitute these multi-cycle paths and false paths. A multi-cycle path is a logic path where the timing requires more than a single clock cycle to determine the result. For example, from a flip flop output to the next flip flop's input, the logic calculation time in the path is more than a single clock cycle. There can be multi-cycle paths which are two, three, or even more clock cycles in length. In other words, a multi-cycle path in a sequential circuit is a path that does not have to propagate signals in a single clock cycle. A false path is one where a certain path through the logic can never be encountered during actual operation. Due to control logic and the functional logic, a calculation may never have a certain path exercised. Both multi-cycle paths and false paths can have state machines (SM) that control them. State machines are also referred to as Finite State Machines (FSM) where the number of states, transitions between the states, and the actions performed are finite. One problem is that multi-cycle paths and false paths can consume power uselessly because they can consume power without providing a function calculation.